128X64 OLED via I2C using STM32F103C8Tx microcontroller.
STM32F103C8Tx <-> I2C <-> OLED 128X64 Documentation
By: Nachiketh V Boin
-Hardware Components and
PC Requirements
>STM32F103C8Tx Board.
> OLED 128X64 I2C SSD1306.
>PC
with STM32CubeIde (CubeIDE Link)
, Bread Board and connectors.
-Hardware
Connections
>5V
PIN of STM32 > VCC PIN of 128X64 OLED SSD1306
>G
PIN of STM32 > GND PIN of 128X64 OLED SSD1306
>PB8
PIN of STM32 > SCL PIN of 128X64 OLED SSD1306
>PB9
PIN of STM32 > SDA PIN of 128X64 OLED SSD1306
-Pinout and Configuration
> A_>Z
·
RCC > Mode
> High Speed Clock (HSE) >
Crystal/Ceramic Resonator (clock from external crystal).
>Low Speed Clock (LSE) >
Disable.
·
I2C1 > Mode
> I2C >
I2C (Note: Pin PB6 > I2C SCL, Pin PB7 > I2C SDA)
·
I2C Parameter
Settings > Master Features
> I2C Speed Mode > Fast Mode
>I2C Clock Speed(Hz) > 400000
Rest all default
·
SYS > Mode
> Debug > Serial Wire (select
serial wire debug or else the ST link will not work after the first flash and
to make it work again you have to erase
it).
> Timebase Source > SysTick.
-Clock Configuration
SSD1306
D[7:0] IO
These are 8-bit bi-directional data bus to be connected to
the microprocessor’s data bus. When serial interface mode is selected, D0 will
be the serial clock input: SCLK; D1 will be the serial data input: SDIN and D2
should be kept NC. When I2 C mode is selected, D2, D1 should be tied together
and serve as SDAout, SDAin in application and D0 is the serial clock input,
SCL.
SSD1306 OLED display
Introduction
- OLED is
Organic Light Emitting Diode that emits light in
response to an electric current. OLED display works with no backlight so
it can display deep black levels. It is small in size and light in weight
than Liquid Crystal Displays.
- 128x64
OLED display is simple dot matrix graphic display. It has 128 columns and
64 rows which make it display of total 128x64 = 8192 pixels.
By just turning on/off these pixel’s led we can display a graphical image
of any shape on it.
128x64 OLED Display
OLED
displays driven by SSD1306 driver IC. SSD1306 is a CMOS OLED driver with
controller for OLED dot-matrix graphic display system. Due to use of SSD1306
driver, number of external components required and power consumption has
reduced.
- OLED
display is used for displaying text, images and various patterns. It is
also suitable for mobile phone sub-display, MP3 player, calculators etc.
- OLED
display has 256 steps for brightness control.
- OLED
display also available with different resolution like 128x32, 128x64. OLED
display in above image has resolution of 128x64 pixels.
Available
Interfaces for OLED
OLED
display module can be interfaced with microcontrollers using three interfaces
given below:
6800/8000
series compatible Parallel Interface
In this interface
8-bit data send/receive could be done through parallel lines i.e. D0-D7.
I2C
interface
In this interface,
data send/receive could be done serially through SDA line.
Serial
Peripheral Interface
In this interface,
data send/receive could be done serially through SDI and SDO lines.
Note: The
module illustrated here has I2C interface pins so all the discussion below is
considering I2C as interfacing standard.
There
are different types of OLED modules are available in market, having different
resolutions, communication protocol (as discussed in above Available
Interfaces for OLED section) and pixel colours (e.g. blue, yellow,
white). Some modules support multi-colours as well.
OLED Display Pins (I2C interface)
OLED
Display Pins
SDA
(Serial Data):
SDA is used to
transmit data between master and slave. The data and acknowledgment are sent
through SDA.
SCL
(Serial Clock):
It is a clock signal.
This pin transmits clocks to slave, SCL. Data will be sent to other devices on
clock tick event. Only master device has control over this SCL line
VCC:
This is power supply
pin. +3.3V supply is required. More than 3.3 V supply can damage the display.
GND:
This is Ground pin.
Connect ground of supply to this pin.
I2C
Address of OLED display
In
I2C interface devices are recognized by their slave address. OLED display has
slave address format as shown in below image.
SA0(Slave
Address) bit:
- This
bit provides two slave address option to choose from.
R/W
(Read/Write) bit:
- This
bit is used to determine mode of operation i.e. I2C write or I2C read
operation. 1 for read operation and 0 for write operation.
Now
if SA0 bit is 0, then microcontroller can do
read/write operation with OLED display using below I2C address.
- I2C
write address is 0x78 (b01111000)
- I2C
read address is 0x79 (b01111001)
Display Structure
OLED
Display is mapped with GDDRAM of SSD1306.
GDDRAM pages structure of SSD1306
The
GDDRAM (Graphics Display Data RAM) is a bit mapped static RAM. It holds the bit
pattern to be displayed.
Pixelwise structure of OLED Display
- The
size of GDDRAM is 128 x 64 bits and it is divided into eight pages, from
PAGE0 to PAGE7, which are used for monochrome 128x64 dot matrix display as
shown in above figure.
- When a
data byte (D0-D7) is written into GDDRAM, all the rows data pixels of the
same page of the current column gets filled. Data bit D0 is written on the
top row, while data bit D7 is written into bottom row as shown in Figure
Row
and Column Mapping on OLED
- Display
has total 8 pages, 64 rows and 128 Columns.
- Each
page contains of 8 rows and 128 columns as shown in above figure.
- Display
has total 128 columns called as segments.
- For
displaying data at first location set page address to 0 and column address
to 0. We should also select the end address of page and column.
- Maximum
end address of page is 07H and Maximum column address is 7F H.
Commands for SSD1306
Note:
Commands and initialization sequence given here is generalized and it worked
for us.
Set
Display Clock Divide Ratio/ Oscillator Frequency (0xD5 h):
- Bit 3
to 0: Display Clock Divide Ratio (D) Set the divide ratio to generate DCLK
(Display Clock) from CLK. The divide ratio is from 1 to 16, with reset
value = 1.
- Bit 7
to 4: Set oscillator frequency. The 4-bit value results in 16 different
frequency settings. The default setting is 1000b.
Set
Multiplex Ratio (0xA8 h):
- This
command switches the default 63 multiplex mode to any multiplex ratio,
ranging from 16 to 63.
Set
Display Start Line (0x40 H~0x7F H):
- This
command sets the Display Start Line register to determine starting address
of display RAM, by selecting a value from 0 to 63. In our program we set
this to zero and map RAM row 0 to COM 0.
Set
Memory Addressing Mode (0x20 H):
There
are three different addressing modes in SSD1306:
- Page
addressing mode
- Horizontal
addressing mode
- Vertical
addressing mode
1.
Page Addressing Mode:
·
In page addressing mode, after the
display RAM is read/written, the column address pointer is increased
automatically by 1.
·
If the column address pointer reaches
column end address, the column address pointer is reset to column start address
but page address pointer not points to next page.
·
Hence, we need to set the new page and
column addresses in order to access the next page RAM content.
·
We need to set lower two bits to ‘1’
and ‘0’ for Page Addressing Mode.
Address
Pointer Movement of Page addressing mode
In page addressing
mode, the following steps are required to define the starting RAM access
pointer location:
- Set the
page start address of the target display location by command B0h to B7h.
- Set the
lower start column address of pointer by command 00h~0Fh.
- Set the
upper start column address of pointer by command 10h~1Fh.
For
example, if the page address is set to B2h, lower column address is 03h and
upper column address is 10h, then that means the starting column is SEG3 of
PAGE2. The RAM access pointer is located as shown in Figure. The input data
byte will be written into RAM position of column 3.
2.
Horizontal Addressing Mode:
- In
horizontal addressing mode, after the display RAM is read/written, the
column address pointer is increased automatically by 1.
- If the
column address pointer reaches column end address, the column address
pointer is reset to column start address and page address pointer is
increased by 1.
- When
both column and page address pointers reach the end address, the pointers
are reset to column start address and page start address
- We need
to set last two digits to ‘0’ and ’0’ for horizontal addressing
mode.
Address
Pointer Movement of Horizontal addressing mode
3.Vertical
Addressing Mode:
- In
vertical addressing mode, after the display RAM is read/written, the page
address pointer is increased automatically by 1.
- If the
page address pointer reaches the page end address, the page address
pointer is reset to page start address and column address pointer is
increased by 1.
- When
both column and page address pointers reach the end address, the pointers
are reset to column start address and page start address.
- We need
to set last two digits to ‘0’ and ’1’ for vertical addressing mode.
Address
Pointer Movement of Vertical addressing mode
In normal display
data RAM read or write and horizontal/vertical addressing
mode, the following steps are required to define the RAM access pointer
location:
- Set the
column start and end address of the target display location by command
21h.
- Set the
page start and end address of the target display location by command 22h.
Set
Column Address (0x21 H):
- This is
a triple byte command. First byte specifies the command for setting column
address (0x21 H).
- Second
byte specifies the column start address and third byte specifies column
end address.
- This
command also sets the column address pointer to column start address.
Set
Page Address (0x22 H):
- This is
a triple byte command. First byte specifies the command for setting page
address (0x22 H).
- Second
byte specifies page start address and third byte is page end address.
- This
command also sets the page address pointer to page start address.
Example
of column and row address pointer movement:
In
the following example, Horizontal addressing mode is used. Column start address
is set to 2 and column end address is set to 125.
- Page
start address is set to 1 and end address is set to 6. In this case, the
graphic display data RAM column accessible range is from column 2 to
column 125 and from page 1 to page 6 only.
- In
addition, the column address pointer is set to 2 and page address pointer
is set to 1. After finishing read/write one pixel of data, the column
address is increased automatically by 1 to access the next RAM location
for next read/write operation.
- Whenever
the column address pointer finishes accessing the end column 125, it gets
reset back to the column 2 and page address is automatically increased by
1.
- While
the end page 6 and end column 125 RAM location is accessed, the page
address gets reset back to 1 and the column address is reset back to 2.
Set
Contrast Control (0x81 H):
- This
command sets the Contrast Setting of the display. The chip has 256
contrast steps from 00h to FF H. The segment output current
increases as the contrast step value increases.
Set
Pre-charge period (0xD9 H):
- This
command is used to set the duration of the pre-charge period. The interval
is counted in number of DCLK, where RESET equals 2 DCLKs.
Set
VCOMH Deselect Level (0xDB H):
- This
command adjusts the VCOMH regulator output.
Entire
display on (0xA4 H/0xA5 H):
- A4 h
command resumes the display from entire display “ON” stage.
- A5 h
command forces the entire display to be “ON”, regardless of the contents
of the display data RAM.
Set
Normal/Inverse Display (0xA6h/0xA7h):
- A6 h
command is for normal display.
- A7 h
command is for inverse display.
Set
Display ON/OFF (0xAE H/0xAF H):
- AE h:
Set display OFF.
- AF
h: Set display ON
Fonts Driver
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